High density integrated circuit memories have density dominated by cell size; thus alternative capacitor dielectrics such as high dielectric constant para-electrics for dynamic memory (DRAM) and ferroelectrics for nonvolatile ferroelectric memory (FeRAM) have received intense investigation. The para-electrics currently being investigated barium strontium titanate (BST) and tantalum pentoxide and the ferro electrics include strontium bismuth tantalite (SBT) and lead zirconate titanate (PZT).
Currently there is a need to increase the packing density and reliability of ferroelectric memory integrated circuits. A cross-section of a portion of a typical ferroelectric memory cell is shown in FIG. 1. In a typical 1T-1C ferroelectric memory cell a ferroelectric memory capacitor is connected to a bit line through a MOS transistor. Shown in FIG. 1 is the,memory capacitor 160 and MOS transistor from such a 1T-1C memory cell. The MOS transistor comprises a gate dielectric layer 30 on a semiconductor 10. A gate electrode layer 40 is formed on the gate dielectric layer 30 and dielectric sidewall structures 50 are formed adjacent to the gate structure 40. Source and drain regions 60 are formed in the semiconductor 10 adjacent the gate layer 40. Isolation structures 20 are formed in the semiconductor 10 and can comprise shallow trench isolation (STI) similar to that shown in FIG. 1. Following the formation of the MOS transistor, a dielectric layer 70 is formed over the MOS transistor.
In fabricating the ferroelectric capacitor 160 portion of the memory cell, a metal contact 80 (usually comprising tungsten) is formed in the dielectric layer 70. The metal contact 70 provides an electrically conductive path connecting the drain/source 60 of the MOS transistor to one of the plates of the ferroelectric capacitor 160. Following the formation of the metal contact 80, layers of titanium aluminum nitride (TiAlN) 90, iridium (Ir) 100, lead zirconate titanate (PZT) 110, iridium (Ir) 120, and titanium aluminum nitride (TiAlN) 130 are formed and patterned resulting in the ferroelectric capacitor 160. A dielectric layer 140 can then be formed over the capacitor structure and a metal contact 150 provided to connect to the other capacitor plate. In the structure shown in FIG. 1, the PZT layer 110 functions as the capacitor ferroelectric layer and the Ir layers 100 and 120 both function as plates for the capacitor. The TiAlN layers 90 and 130 function as barrier layers. In patterning the various layers to form the ferroelectric capacitor 160, plasma etch process are used to etch the various layers. The plasma etch processes currently in use result in the 68° to 73° tapered ferroelectric capacitor profile shown in FIG. 1. The tapered capacitor profiles limit the packing density of the circuits that are formed using tapered ferroelectric capacitors. In addition the resulting leakage current through the ferroelectric capacitor is higher than desirable due to electrical shorts formed during the etching process. There is therefore a need for an improved method to form ferroelectric capacitors. The instant invention addresses this need.